`include "ctrl_encode_def.v"
`include "ctrl_encode_def.v"
module NPC(Reg, ID_PC, EX_PC, NPCOp, EX_ALUOp, IMM, EX_IMM,
	NPC, PCSrc, aluDataIn1, aluDataIn2, 
	IFID_Flush, IDEX_Flush, PCPLUS4
);  // next pc module

	input      [31:0]      Reg; 
	input      [31:0]    ID_PC;
	input      [31:0]    EX_PC;      // pc
	input       [1:0]    NPCOp;      // next pc operation
	input       [4:0] EX_ALUOp;
	input      [25:0]      IMM;      // immediate
	input      [25:0]   EX_IMM;
	input    [31:0] aluDataIn1;
	input    [31:0] aluDataIn2;
	input    [31:0]    PCPLUS4;
	output reg [31:0]      NPC;      // next pc
	output reg           PCSrc;
	output reg      IFID_Flush;
	output reg      IDEX_Flush;

	wire     [31:0] ID_PCPLUS4;
	wire     [31:0] EX_PCPLUS4;
	
	assign EX_PCPLUS4 = EX_PC + 4;
	assign ID_PCPLUS4 = ID_PC + 4;

	always @(EX_ALUOp, NPCOp, aluDataIn1, aluDataIn2) begin

				if (((aluDataIn1 == aluDataIn2) && (EX_ALUOp == `ALUOp_EQL)) || 
				((aluDataIn1 != aluDataIn2) && (EX_ALUOp == `ALUOp_BNE)))
				begin
					NPC = EX_PCPLUS4 + {{14{EX_IMM[15]}}, EX_IMM[15:0], 2'b00};
					PCSrc = 1;
					IFID_Flush = 1;
					IDEX_Flush = 1;
				end

				else if (NPCOp == `NPC_JUMP)
				begin
					NPC = {ID_PCPLUS4[31:28], IMM[25:0], 2'b00};
					PCSrc = 1;
					IFID_Flush = 1;
					IDEX_Flush = 0;
				end

				else if (NPCOp == `NPC_JR)
				begin
					NPC = Reg;
					PCSrc = 1;
					IFID_Flush = 1;
					IDEX_Flush = 0;
				end

				else
				begin
					NPC = PCPLUS4;
					PCSrc = 0;
					IFID_Flush = 0;
					IDEX_Flush = 0;
				end

	end
		
endmodule